The conventional dual in-line package (DIP) comprises an elongate lead frame with, for example, up to forty or more pins or leads arranged in dual parallel rows. The integrated circuit chip or die is attached by bonding to a "paddle" supported at the center of the lead frame by paddle support fingers. Lead frame fingers or traces including a power lead finger, ground lead finger, and signal lead fingers extend radially from the open perimeter around the paddle to the dual parallel rows of pins. The fingers and leads or pins generally comprise unitary conductive paths which, in the DIP may extend for considerable length from the center of the lead frame to the elongate ends. The entire package, except leads, is enclosed in encapsulation molding compound and a flow coating may be formed and cured over the die for environmental protection of the die prior to encapsulation molding.
The long parallel lines or runs of adjacent conductive strips or traces formed by the lead frame fingers extending to the elongate ends particularly in larger DIP'S exhibit substantial inductance and inductive coupling and may result in high inductive impedance to signal currents. The long ground lead to the end of the DIP is particularly vulnerable in this respect because of the relatively large currents which must pass through the ground lead to or from multiple signal leads. The inductive impedance significantly retards signal propagation causing signal delay, and "ground bounce" from rapid ground current changes following transients at either the power lead V.sub.cc or the signal leads. The inductive coupling between long lines of the standard DIP also results in cross talk or cross coupling between signals and consequent noise.
As explained, for example, in "The Impact of Inductance on Semiconductor Packaging", by Leonard W. Schaper, Bell Laboratories, Murray Hill, New Jersey, published in the First Annual Conference of the International Electronics Packaging Society (IEPS), Cleveland, Ohio, pp. 38-43, November 9-10, 1981, the major inductance problem is in the power and ground leads, since these carry the large transient currents generated by the switching of many logic circuit gates at once. Furthermore, the different logic circuit gates of the chip or die have different transient characteristics. The inductance of the lead frame fingers is proportional to the length and inversely proportional to the width of the traces. The inductance of the leads or traces leading to the power supply and ground at the ends of the DIP are so great that it may be impossible for significant leading edge current to come from the supply. As a result, bypass capacitors in the external circuitry may be used to supply current. Current transients in the lead or trace inductors between the decoupling capacitor and the power supply produce transient voltage drops which applied across the capacitors generate the desired leading edge switching current. Generally such bypass capacitors are located outside the package in the external circuitry.
A disadvantage of the use of external bypass or decoupling capacitors is that the capacitors must also compensate for the inductance of leads and circuits at the external circuitry associated with the DIP package. Another disadvantage of the external decoupling capacitor is that the decoupling capacitor is between the power supply lead and ground only and can not compensate for inductances when the current transient is between the multiple signal leads and ground.
With increased switching speeds and rate of current change, the transient voltages and consequent inductive impedance in the leads or traces also increases. Greater use of parallel architecture and common bus architecture in the integrated circuits also increases the number of logic circuit gates changing simultaneously thereby increasing the transient voltages across the leads and the effect of inductive reactance. The result is even slower useable signal speed propagation, and increased "ground bounce" from rapid ground current changes caused by the power supply or signal leads.
Another disadvantage of conventional DIP packaging is the slow dissipation or removal of heat generated at the chip or die as a result of the relatively high thermal resistance of the packaging material. Heat generated on the surface of the die passes through the encapsulation molding material to ambient air and through the leads and prongs. Heat removal problems result in a hot spot in the center of the packaging shortening the life of the integrated circuit chip or die. As a general rule, the life of the device is, for example, halved for each 10.degree. C. increase in operating temperature.
For more complex chips such as a microprocessor in a longer package with, for example, forty pins or leads, a high thermal conductivity heat spreader such as a metal heat plate may be inserted below the lead frame in the encapsulation molding compound material. As a general rule, however, the heat generated at the die must still pass through a layer of molding compound to the heat spreader. Such heat spreaders are described, for example, by James A. Andrews, L. M. Mahalingam, and Howard M. Berg, "Thermal Characteristics of 16 and 40 PIN Plastic DlL Packages", IEEE (1981) (Publication CH 1671-7/81/0000-0136). Such a heat spreader may conduct heat from just below the chip over the entire area of the lead frame package.
These thermal characteristics of low heat dissipation and the electrical characteristics of slow signal speed, ground bounce, and noise, limit the applicability and usefulness of DIP packaging for the faster bipolar chips. Because of these limitations, the traditional DIP packaging is unable to match the faster chip technology now available.